Semiconductor devices are manufactured by forming active regions in a semiconductor substrate, depositing various insulating, conductive, and semiconductive layers over the substrate, and patterning them in sequential steps. The upper or last-formed layers of the semiconductor device typically comprise metallization layers. The metallization layers typically comprise one or more layers of metal interconnect having conductive lines disposed within an insulating material, and may provide connections to underlying active regions and connections within and over the substrate.
As the cost of shrinking semiconductor devices continues to increase, alternative approaches, such as extending the integration of circuits into the third dimension or semiconductor substrate stacking are being explored. Two or more substrates are bonded together to form a three-dimensional structure.
FIG. 1 illustrates a prior art structure for bonding substrates. Top die 102 is bonded to bottom substrate 104 employing bumps 110. Further bottom substrate 104 comprises through substrate vias (TSVs) 112, and top die 102 comprises Cu/Ni pads 108. Bump 110 is a eutectic solder micro-bump joint implemented to bond the Cu surfaces. In solder bump interconnects, solder wetting onto bond pads is a key factor that determines the interconnect process yield and the solder joint reliability. Solder wetting involves various physical attributes such as surface tension imbalance, viscous dissipation, molecular kinetic motion, chemical reaction, and diffusion. The degree of wetting may be described by the contact angle, the angle at which the liquid interface meets the solid interface. The degree of wetting between Cu and conventional eutectic solder may not be optimum. If the wetting is poor, the solder may form a compact droplet on the copper surface, leaving insufficient area bonded between the copper and the eutectic solder.
Further solder joint reliability may be a problem in that copper easily oxidizes and may oxidize during the solder process. Moreover, the relatively large size of the solder bumps 110, which may be in the range of tens of μms and greater, is not conducive to shrinking devices.